This paper presents two wideband fractional-N frequency synthesizers designed in a 0.13-μm CMOS technology for software-defined radio applications. The first synthesizer adopts a quadrature voltage-controlled oscillator (QVCO) with a new phase shifter scheme, which shows better phase noise performance and more stable oscillation. Combining harmonic rejection and single sideband mixing, a harmonic-rejection SSBmixer (HR-SSBmixer) is developed to suppress unwanted sidebands and spurious signals. The HR-SSBmixer serves as a power-saving solution to generate the local oscillator (LO) signal for the 802.11a standard by avoiding power-hungry poly-phase filters or high-frequency LO buffers and dividers. The second synthesizer adopts a dual-mode voltage-controlled oscillator (DMVCO). The DMVCO allows the synthesizer to leverage single-sideband mixing, a power efficient approach, for high-frequency LO signal generation. When compared to the QVCO approach, the DMVCO solution allows the synthesizer to provide continuous LO signals without frequency gaps. Both synthesizers support wireless standards including DVB-T, GSM, WCDMA, TDSCDMA, WLAN802.11 a/b/g and Bluetooth. The measurement results show that the synthesizers' frequency range, phase noise, settling time and the spur performances meet the design specifications of the standards mentioned above. The QVCO-based synthesizer occupies an active area of 1.86 mm2 and consumes 35 to 52 mW of power, while the DMVCO-based synthesizer occupies an area of 2.3 mm2 and consumes 34 to 77 mW of power.