Abstract
This paper describes the use of moderate inversion for selected MOS transistors in a two-stage CMOS amplifier to achieve high voltage gain, low thermal noise, and fast settling time at minimum power consumption. A detailed circuit analysis, implemented in a MATLAB design tool, is presented to find the optimal inversion level for MOS transistors. The analysis and design tool are illustrated for a fully differential, two-stage, 0.5-μm CMOS amplifier having voltage gain > 80 dB, input-referred thermal noise voltage < 6 nV/Hz 1/2, gain bandwidth of 100 MHz, phase margin of 58°, and 0.1% settling time < 15 ns for load capacitances of 6 pF and a supply voltage of 2.5 V. SPICE simulation results confirm that these specifications are achieved at a minimum supply current of 2.42 mA by operating first-and second-stage input transistors in moderate inversion compared to 3.82 mA for operation in strong inversion, resulting in a 37% decrease in power consumption.
Original language | English |
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Pages | 432-435 |
Number of pages | 4 |
DOIs | |
State | Published - 2012 |
Event | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: May 20 2012 → May 23 2012 |
Conference
Conference | 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 |
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Country/Territory | Korea, Republic of |
City | Seoul |
Period | 05/20/12 → 05/23/12 |