The power efficiency of the final stage power amplifier (PA) in a RF transmitter is critical for the overall power consumption, size, lifetime, and reliability of RF transceiver products, especially for portable low-power highly-integrated RF-SoC applications. This paper discusses the limitations and issues in applying the analytic design equations for designing highly efficient RF Class E PAs. The main focus of this work is on the validation of the previously published analytic design equations for optimal Class E PAs design, as we implemented the PA designs using both discrete RF transistors and monolithic RF ICs at 300 to 2400 MHz. It is found that these analytic design equations available in the literature for RF Class E PAs design largely ignored some important physical factors such as the bias sensitivity for the transistor, the undesired device parasitics at RF frequencies, the finite inductance and the low quality factor of the RF choke and/or tank inductors, the time-varying input impedance, and PA stability, etc. They are therefore in general not adequate for predicting the optimal Class E PA performance at RF frequencies.