Suitability of N-ON Recessed Implanted Gate Vertical-Channel SiC JFETs for Optically Triggered 1200 V Solid-State Circuit Breakers

Victor Veliadis, Brian Steiner, Kevin Lawson, Stephen Bayne, D Urciuoli, H Ha

Research output: Contribution to journal › Article › peer-review

Original language	English
Pages (from-to)	874–879
Journal	IEEE Journal of Emerging and Selected Topics in Power Electronics
State	Published - 2016

Cite this

@article{d4ee957eeb2c4eb7a14f8bf48b4b80eb,

title = "Suitability of N-ON Recessed Implanted Gate Vertical-Channel SiC JFETs for Optically Triggered 1200 V Solid-State Circuit Breakers",

author = "Victor Veliadis and Brian Steiner and Kevin Lawson and Stephen Bayne and D Urciuoli and H Ha",

year = "2016",

language = "English",

pages = "874–879",

journal = "IEEE Journal of Emerging and Selected Topics in Power Electronics",

}

TY - JOUR

T1 - Suitability of N-ON Recessed Implanted Gate Vertical-Channel SiC JFETs for Optically Triggered 1200 V Solid-State Circuit Breakers

AU - Veliadis, Victor

AU - Steiner, Brian

AU - Lawson, Kevin

AU - Bayne, Stephen

AU - Urciuoli, D

AU - Ha, H

PY - 2016

Y1 - 2016

M3 - Article

SP - 874

EP - 879

JO - IEEE Journal of Emerging and Selected Topics in Power Electronics

JF - IEEE Journal of Emerging and Selected Topics in Power Electronics

ER -