Data prefetching is widely adopted in modern high performance processors to bridge the ever-increasing performance gap between processor and memory. Many prefetching techniques have been proposed to exploit patterns among data access history that is stored in on-chip hardware table. We demonstrate that the table size has considerable impact on the performance of data prefetching. While a small table size limits the effectiveness of the prediction due to inadequate history, a large table is expensive to be implemented on-chip and has longer latency. It is critical to find a storage-efficient data prefetching mechanism. We propose a novel Dynamic Signature Method (DSM) that stores the addresses efficiently to reduce the demand of storage for prefetching. We have carried out extensive simulation testing with a trace-driven simulator, CMP$im, and SPEC CPU2006 benchmarks. Experimental results show that the new DSM based prefetcher achieved better performance improvement for over half benchmarks compared to the existing prefetching approaches with the same storage consumption.