Sample clock offset detection and correction in the LTE downlink

Elliot Briggs, Brian Nutter, Dan McLane

Research output: Contribution to journalArticle

Abstract

The narrow subcarrier spacing and wide bandwidth arrangement in the LTE downlink produce a vulnerability to sample clock mismatch between the transmitting and receiving data converters. Without high precision sampling clock frequencies, a high level of inter-carrier interference (ICI) is introduced, yielding undesirable performance. In this article, a method to jointly estimate and correct sampling frequency mismatch is proposed. The proposed method uses information already known to the receiver, operates strictly in the time domain and does not require the aid of pilot symbols or other frequency domain information. The method allows clocks with lower precision to be used with minimal performance degradation. Results are presented using MATLAB simulation as well as an FPGA hardware implementation.

Original languageEnglish
Pages (from-to)31-39
Number of pages9
JournalJournal of Signal Processing Systems
Volume69
Issue number1
DOIs
StatePublished - Oct 2012

Keywords

  • FPGA
  • ICI
  • LTE
  • OFDM
  • Sample clock offset

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