Pressure-driven hardware managed thread concurrency for irregular applications

John D. Leidel, Xi Wang, Yong Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Given the increasing importance of efficient data intensive computing, we find that modern processor designs are not well suited to the irregular memory access patterns found in these algorithms. This research focuses on mapping the compiler's instruction cost scheduling logic to hardware managed concurrency controls in order to minimize pipeline stalls. In this manner, the hardware modules managing the low-latency thread concurrency can be directly understood by modern compilers. We introduce a thread context switching method that is managed directly via a set of hardwarebased mechanisms that are coupled to the compiler instruction scheduler. As individual instructions from a thread execute, their respective cost is accumulated into a control register. Once the register reaches a pre-determined saturation point, the thread is forced to context switch. We evaluate the performance benefits of our approach using a series of 24 benchmarks that exhibit performance acceleration of up to 14.6X.

Original languageEnglish
Title of host publicationProceedings of IA3 2017
Subtitle of host publication7th Workshop on Irregular Applications: Architectures and Algorithms, Held in conjunction with SC 2017: The International Conference for High Performance Computing, Networking, Storage and Analysis
PublisherAssociation for Computing Machinery, Inc
ISBN (Electronic)9781450351362
DOIs
StatePublished - Nov 12 2017
Event7th Workshop on Irregular Applications: Architectures and Algorithms, IA3 2017 - Denver, United States
Duration: Nov 12 2017Nov 17 2017

Publication series

NameProceedings of IA3 2017: 7th Workshop on Irregular Applications: Architectures and Algorithms, Held in conjunction with SC 2017: The International Conference for High Performance Computing, Networking, Storage and Analysis

Conference

Conference7th Workshop on Irregular Applications: Architectures and Algorithms, IA3 2017
CountryUnited States
CityDenver
Period11/12/1711/17/17

Keywords

  • Data intensive computing
  • Irregular algorithms
  • Thread concurrency

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    Leidel, J. D., Wang, X., & Chen, Y. (2017). Pressure-driven hardware managed thread concurrency for irregular applications. In Proceedings of IA3 2017: 7th Workshop on Irregular Applications: Architectures and Algorithms, Held in conjunction with SC 2017: The International Conference for High Performance Computing, Networking, Storage and Analysis [3149705] (Proceedings of IA3 2017: 7th Workshop on Irregular Applications: Architectures and Algorithms, Held in conjunction with SC 2017: The International Conference for High Performance Computing, Networking, Storage and Analysis). Association for Computing Machinery, Inc. https://doi.org/10.1145/3149704.3149705