PIMS: A lightweight processing-in-memory accelerator for stencil computations

Jie Li, Xi Wang, Antonino Tumeo, Brody Williams, John D. Leidel, Yong Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations


Stencil computation is a classic computational kernel present in many high-performance scientific applications, like image processing and partial differential equation solvers (PDE). A stencil computation sweeps over a multi-dimensional grid and repeatedly updates values associated with points using the values from neighboring points. Stencil computations often employ large datasets that exceed cache capacity, leading to excessive accesses to the memory subsystem. As such, 3D stencil computations on large grid sizes are memory-bound. In this paper we present PIMS, an in-memory accelerator for stencil computations. PIMS, implemented in the logic layer of a 3D-stacked memory, exploits the high bandwidth provided by through-silicon vias to reduce redundant memory traffic. Our comprehensive evaluation using three different grid sizes with six categories of orders indicate that the proposed architecture reduces 48.25% of data movement on average and obtains up to 65.55% of bank conflict reduction.

Original languageEnglish
Title of host publicationMEMSYS 2019 - Proceedings of the International Symposium on Memory Systems
PublisherAssociation for Computing Machinery
Number of pages12
ISBN (Electronic)9781450372060
StatePublished - Sep 30 2019
Event2019 International Symposium on Memory Systems, MEMSYS 2019 - Washington, United States
Duration: Sep 30 2019Oct 3 2019

Publication series

NameACM International Conference Proceeding Series


Conference2019 International Symposium on Memory Systems, MEMSYS 2019
Country/TerritoryUnited States


  • High Performance Computing
  • Hybrid Memory Cube
  • Processing-in-memory
  • Stencil Computation


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