Parallel-DFTL: A flash translation layer that exploits internal parallelism in solid state drives

Wei Xie, Yong Chen, Philip C. Roth

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

Solid State Drives (SSDs) using flash memory storage technology present a promising storage solution for data-intensive applications due to their low latency, high bandwidth, and low power consumption compared to traditional hard disk drives. SSDs achieve these desirable characteristics using internal parallelism - parallel access to multiple internal flash memory chips - and a Flash Translation Layer (FTL) that determines where data is stored on those chips so that they do not wear out prematurely. Unfortunately, current state-of- the-art cache-based FTLs like the Demand-based Flash Translation Layer (DFTL) do not allow IO schedulers to take full advantage of internal parallelism because they impose a tight coupling between the logical-to-physical address translation and the data access. In this work, we propose an innovative IO scheduling policy called Parallel-DFTL that works with the DFTL to break the coupled address translation operations from data accesses. Parallel-DFTL schedules address translation and data access operations separately, allowing the SSD to use its flash access channel resources concurrently and fully for both types of operations. We present a performance model of FTL schemes that predicts the benefit of Parallel-DFTL against DFTL. We implemented our approach in an SSD simulator using real SSD device parameters, and used trace-driven simulation to evaluate its efficacy. Parallel-DFTL improved overall performance by up to 32% for the real IO workloads we tested, and up to two orders of magnitude for our synthetic test workloads. It is also found that Parallel-DFTL is able to achieve reasonable performance with a very small cache size.

Original languageEnglish
Title of host publication2016 IEEE International Conference on Networking Architecture and Storage, NAS 2016 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509033157
DOIs
StatePublished - Aug 23 2016
Event11th IEEE International Conference on Networking Architecture and Storage, NAS 2016 - Long Beach, United States
Duration: Aug 8 2016Aug 10 2016

Publication series

Name2016 IEEE International Conference on Networking Architecture and Storage, NAS 2016 - Proceedings

Conference

Conference11th IEEE International Conference on Networking Architecture and Storage, NAS 2016
CountryUnited States
CityLong Beach
Period08/8/1608/10/16

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    Xie, W., Chen, Y., & Roth, P. C. (2016). Parallel-DFTL: A flash translation layer that exploits internal parallelism in solid state drives. In 2016 IEEE International Conference on Networking Architecture and Storage, NAS 2016 - Proceedings [7549413] (2016 IEEE International Conference on Networking Architecture and Storage, NAS 2016 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NAS.2016.7549413