Severe hot-carrier degradation has been observed in deep-submicron N-MOSFETs, and it is shown to be caused by several advanced device processing steps. These processing steps can also introduce significant changes in other device parameters such as the threshold voltage and transconductance, etc., for devices without any hot-carrier stress. Two major achievements of this work are: (1) We systematically illustrate that the process-induced lifetime degradation is most sensitive to details of back-end wafer processing, particularly when it involves high-density-plasma (HDP-CVD) oxide deposition and H2 annealing; (2) We demonstrate experimentally, for the first time, that using a properly designed SiN Pre-Metal-Dielectric (PMD) liner process can most effectively stop the back-end process-induced lifetime degradation. This result is different from previous reports which indicated that an additional SiN liner could further degrade the device lifetime [1-3]. We will show that this apparent inconsistency is partly because one needs to very careful in designing the liner process to make it work properly, and partly because the previous studies did not cover the back-end process-induced hot-carrier effects.