This paper describes novel RF Built-in Self Test (RF-BiST) and RF Built-in-Self-Calibration (RF-BiSC) techniques that can test the performance of RF SoC's using on-chip resources as both test stimuli and response analyzers. Our RF-BiST approach is to fully utilize existing on-chip circuitry to prevent adding extra die area, while remaining capable of performing various RF-SoC self-tests. Successful RF-BiST examples include internally measuring RF oscillators with on-chip digital signals from an All-Digital Phase Locked Loop (ADPLL). Other RF-BiST examples cover various contributors to Error Vector Magnitude (EVM) such as gain, linearity, and phase noise. Functional RF-BiSTs, such as loop-back methods, can be verified from GSM/EDGE to WLAN SoCs through good correlation with comparable external tests. Additionally, RF-BiST/ BiSC with on-chip digital controllers and compensation networks can help drastically reduce the cost of phase and amplitude calibration and the deployment time with improved uniformity for phased-array RADARs, benefiting both future military and commercial RADAR systems considerably.