TY - JOUR
T1 - High-efficiency silicon-based envelope-tracking power amplifier design with envelope shaping for broadband wireless applications
AU - Wu, Ruili
AU - Liu, Yen Ting
AU - Lopez, Jerry
AU - Schecht, Cliff
AU - Li, Yan
AU - Lie, Donald Y.C.
PY - 2013
Y1 - 2013
N2 - This paper presents a highly efficient silicon-based envelope-tracking power amplifier (ET-PA) for broadband wireless applications. A pseudo-differential power amplifier (PA) is designed using two integrated SiGe power cells fabricated in a 0.35-μm SiGe BiCMOS technology with through-silicon-via (TSV). In the continuous-wave (CW) measurement, the PA achieves a saturated output power (Pout) of around 2 W with power-added efficiency (PAE) above 65% across the bandwidth of 0.7-1.0 GHz. To optimize the ET-PA system performance, several envelope shaping methods such as dc shifting, envelope scaling, envelope clipping, and envelope attenuation at back-off have been investigated carefully. A highly efficient monolithic CMOS envelope modulator (EM) integrated circuit (IC) is designed in a 0.35- m bipolar-CMOS-DMOS (BCD) process to mate with our SiGe PA. With the LTE 16 QAM 5/10/20-MHz input signals, our ET-PA system achieves around 28 dBm linear (Pout), passing the stringent LTE linearity specs such as the spectrum emission mask with an average composite system PAE of 42.3%/41.1%/40.2%, respectively. No predistortion is applied in this work.
AB - This paper presents a highly efficient silicon-based envelope-tracking power amplifier (ET-PA) for broadband wireless applications. A pseudo-differential power amplifier (PA) is designed using two integrated SiGe power cells fabricated in a 0.35-μm SiGe BiCMOS technology with through-silicon-via (TSV). In the continuous-wave (CW) measurement, the PA achieves a saturated output power (Pout) of around 2 W with power-added efficiency (PAE) above 65% across the bandwidth of 0.7-1.0 GHz. To optimize the ET-PA system performance, several envelope shaping methods such as dc shifting, envelope scaling, envelope clipping, and envelope attenuation at back-off have been investigated carefully. A highly efficient monolithic CMOS envelope modulator (EM) integrated circuit (IC) is designed in a 0.35- m bipolar-CMOS-DMOS (BCD) process to mate with our SiGe PA. With the LTE 16 QAM 5/10/20-MHz input signals, our ET-PA system achieves around 28 dBm linear (Pout), passing the stringent LTE linearity specs such as the spectrum emission mask with an average composite system PAE of 42.3%/41.1%/40.2%, respectively. No predistortion is applied in this work.
KW - Envelope modulator (EM)
KW - Envelope shaping method
KW - Envelope-tracking (ET)
KW - Long-term evolution (LTE)
KW - SiGe power amplifier (SiGe PA)
KW - Through-silicon-via (TSV)
UR - http://www.scopus.com/inward/record.url?scp=84883299674&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2013.2265501
DO - 10.1109/JSSC.2013.2265501
M3 - Article
AN - SCOPUS:84883299674
SN - 0018-9200
VL - 48
SP - 2030
EP - 2040
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 9
M1 - 6542009
ER -