We have developed a modified bias-dependent Cann's model and performed IC design and hardware experiments to study the linearization of a highly-efficient monolithic quasi-class E SiGe power amplifier (PA) IC using both Envelope-Tracking (ET) and Envelope-Elimination-and-Restoration (EER) techniques. Our simple PA behavior model fits the measured SiGe PA IC data very well across a wide range of bias and supply voltages. Both measurement and simulations show that the ET-linearized PA system is significantly less sensitive to the timing misalignment between the amplitude and the RF signal path than the EER-linearized PA system. Our experimental results also show that ET successfully linearized the SiGe PA to pass the stringent EDGE transmit mask at 900MHz, while EER could not. Simulations also predict that the optimal timing alignment for ET linearization can be achieved at PA base bias voltage V bb=0.55-6V, which is consistent with our measurement results as well.