TY - JOUR
T1 - Energy and Area Efficient Three-Input XOR/XNORs with Systematic Cell Design Methodology
AU - Nikoubin, Tooraj
AU - Grailoo, Mahdieh
AU - Li, Changzhi
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/1
Y1 - 2016/1
N2 - In this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. At first, it is deliberately given priority to general design goals in a base structure of circuits. This structure is generated systematically by employing binary decision diagram. After that, concerning high flexibility in design targets, SCDM aims to specific ones in the remaining three steps, which are wise selections of basic cells and amend mechanisms, as well as transistor sizing. In the end, the resultant three-input XOR/XNORs enjoy full-swing and fairly balanced outputs. They perform well with supply voltage scaling, and their critical path contains only two transistors. They also outperform their counterparts exhibiting 27%-77% reduction in average energy-delay product in HSPICE simulation based on TSMC 0.13-μm technology. The symmetric schematic topologies significantly simplify and minimize the layout, as 26%-32% improvement in area is demonstrated.
AB - In this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension of CDM, plays the essential role in designing efficient circuits. At first, it is deliberately given priority to general design goals in a base structure of circuits. This structure is generated systematically by employing binary decision diagram. After that, concerning high flexibility in design targets, SCDM aims to specific ones in the remaining three steps, which are wise selections of basic cells and amend mechanisms, as well as transistor sizing. In the end, the resultant three-input XOR/XNORs enjoy full-swing and fairly balanced outputs. They perform well with supply voltage scaling, and their critical path contains only two transistors. They also outperform their counterparts exhibiting 27%-77% reduction in average energy-delay product in HSPICE simulation based on TSMC 0.13-μm technology. The symmetric schematic topologies significantly simplify and minimize the layout, as 26%-32% improvement in area is demonstrated.
KW - Binary decision diagram applications
KW - energy efficiency
KW - hybrid-CMOS logic style
KW - systematic design methodology
KW - three-input XOR/XNOR circuits
UR - http://www.scopus.com/inward/record.url?scp=84925856245&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2015.2393717
DO - 10.1109/TVLSI.2015.2393717
M3 - Article
AN - SCOPUS:84925856245
SN - 1063-8210
VL - 24
SP - 398
EP - 402
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 1
M1 - 7067438
ER -