Novel linearity enhancement using body bias tuning for 24-28 GHz CMOS SOI power amplifier (PA) design is reported. The differential PA is designed, laid out, and taped out in an advanced 22nm fully-depleted silicon-on-insulator (FD-SOI) technology, which utilizes stacked FETs, digitally-controlled neutralization capacitors, interstage matching and output matching capacitors with on-chip baluns to cover 24-28 GHz for potential 5G applications. Post-layout SPICE simulations show the AM-PM distortion at Pout,1dB can be reduced to only < 0.1° by body bias tuning of the 2nd stage FETs alone, with power-added-efficiency (PAE) at Pout,1dB at 24.1%/17.5% with high S21 =26.5/22.1 dB at 24GHz/28GHz. Using 64-QAM 250 MHz modulated input signal, this PA design has also achieved an ACLR1 of ~ -24.5/-28.5 dBc at Pout = 11.7/9.5 dBm in post-layout simulation at 28 GHz, and with the smallest core PA die area in the literature. We believe this is the 1st report of very effective AM-PM cancellation for mm-Wave CMOS SOI PA design using positive body biasing.