@inproceedings{b43e0bc8e0604733a759cdbe357b3ae7,
title = "Effective AM-PM cancellation with body bias for 5G CMOS power amplifier design in 22nm FD-SOI",
abstract = "Novel linearity enhancement using body bias tuning for 24-28 GHz CMOS SOI power amplifier (PA) design is reported. The differential PA is designed, laid out, and taped out in an advanced 22nm fully-depleted silicon-on-insulator (FD-SOI) technology, which utilizes stacked FETs, digitally-controlled neutralization capacitors, interstage matching and output matching capacitors with on-chip baluns to cover 24-28 GHz for potential 5G applications. Post-layout SPICE simulations show the AM-PM distortion at Pout,1dB can be reduced to only < 0.1° by body bias tuning of the 2nd stage FETs alone, with power-added-efficiency (PAE) at Pout,1dB at 24.1%/17.5% with high S21 =26.5/22.1 dB at 24GHz/28GHz. Using 64-QAM 250 MHz modulated input signal, this PA design has also achieved an ACLR1 of ~ -24.5/-28.5 dBc at Pout = 11.7/9.5 dBm in post-layout simulation at 28 GHz, and with the smallest core PA die area in the literature. We believe this is the 1st report of very effective AM-PM cancellation for mm-Wave CMOS SOI PA design using positive body biasing.",
keywords = "5G, AM-AM, AM-PM, Body bias, CMOS power amplifier (PA), FD-SOI, Millimeter-wave, Reconfigurable PA",
author = "Mayeda, {Jill C.} and Jerry Tsay and Lie, {Donald Y.C.} and Jerry Lopez",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE Copyright: Copyright 2019 Elsevier B.V., All rights reserved.; null ; Conference date: 26-05-2019 Through 29-05-2019",
year = "2019",
doi = "10.1109/ISCAS.2019.8702159",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings",
}