Effective AM-PM cancellation with body bias for 5G CMOS power amplifier design in 22nm FD-SOI

Jill C. Mayeda; Jerry Tsay; Donald Y.C. Lie; Jerry Lopez

doi:10.1109/ISCAS.2019.8702159

Effective AM-PM cancellation with body bias for 5G CMOS power amplifier design in 22nm FD-SOI

Jill C. Mayeda, Jerry Tsay, Donald Y.C. Lie, Jerry Lopez

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Novel linearity enhancement using body bias tuning for 24-28 GHz CMOS SOI power amplifier (PA) design is reported. The differential PA is designed, laid out, and taped out in an advanced 22nm fully-depleted silicon-on-insulator (FD-SOI) technology, which utilizes stacked FETs, digitally-controlled neutralization capacitors, interstage matching and output matching capacitors with on-chip baluns to cover 24-28 GHz for potential 5G applications. Post-layout SPICE simulations show the AM-PM distortion at Pout,1dB can be reduced to only < 0.1° by body bias tuning of the 2^nd stage FETs alone, with power-added-efficiency (PAE) at Pout,1dB at 24.1%/17.5% with high S21 =26.5/22.1 dB at 24GHz/28GHz. Using 64-QAM 250 MHz modulated input signal, this PA design has also achieved an ACLR1 of ~ -24.5/-28.5 dBc at Pout = 11.7/9.5 dBm in post-layout simulation at 28 GHz, and with the smallest core PA die area in the literature. We believe this is the 1^st report of very effective AM-PM cancellation for mm-Wave CMOS SOI PA design using positive body biasing.

Original language	English
Title of host publication	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728103976
DOIs	https://doi.org/10.1109/ISCAS.2019.8702159
State	Published - 2019
Event	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan Duration: May 26 2019 → May 29 2019

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2019-May
ISSN (Print)	0271-4310

Conference

Conference	2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Country	Japan
City	Sapporo
Period	05/26/19 → 05/29/19

Keywords

5G
AM-AM
AM-PM
Body bias
CMOS power amplifier (PA)
FD-SOI
Millimeter-wave
Reconfigurable PA

Access to Document

10.1109/ISCAS.2019.8702159

Link to publication in Scopus

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Mayeda, J. C., Tsay, J., Lie, D. Y. C., & Lopez, J. (2019). Effective AM-PM cancellation with body bias for 5G CMOS power amplifier design in 22nm FD-SOI. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings [8702159] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2019.8702159

Mayeda, Jill C. ; Tsay, Jerry ; Lie, Donald Y.C. ; Lopez, Jerry. / Effective AM-PM cancellation with body bias for 5G CMOS power amplifier design in 22nm FD-SOI. 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings - IEEE International Symposium on Circuits and Systems).

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title = "Effective AM-PM cancellation with body bias for 5G CMOS power amplifier design in 22nm FD-SOI",

abstract = "Novel linearity enhancement using body bias tuning for 24-28 GHz CMOS SOI power amplifier (PA) design is reported. The differential PA is designed, laid out, and taped out in an advanced 22nm fully-depleted silicon-on-insulator (FD-SOI) technology, which utilizes stacked FETs, digitally-controlled neutralization capacitors, interstage matching and output matching capacitors with on-chip baluns to cover 24-28 GHz for potential 5G applications. Post-layout SPICE simulations show the AM-PM distortion at Pout,1dB can be reduced to only < 0.1° by body bias tuning of the 2nd stage FETs alone, with power-added-efficiency (PAE) at Pout,1dB at 24.1%/17.5% with high S21 =26.5/22.1 dB at 24GHz/28GHz. Using 64-QAM 250 MHz modulated input signal, this PA design has also achieved an ACLR1 of ~ -24.5/-28.5 dBc at Pout = 11.7/9.5 dBm in post-layout simulation at 28 GHz, and with the smallest core PA die area in the literature. We believe this is the 1st report of very effective AM-PM cancellation for mm-Wave CMOS SOI PA design using positive body biasing.",

keywords = "5G, AM-AM, AM-PM, Body bias, CMOS power amplifier (PA), FD-SOI, Millimeter-wave, Reconfigurable PA",

author = "Mayeda, {Jill C.} and Jerry Tsay and Lie, {Donald Y.C.} and Jerry Lopez",

year = "2019",

doi = "10.1109/ISCAS.2019.8702159",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

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Mayeda, JC, Tsay, J, Lie, DYC & Lopez, J 2019, Effective AM-PM cancellation with body bias for 5G CMOS power amplifier design in 22nm FD-SOI. in 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings., 8702159, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2019-May, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, 05/26/19. https://doi.org/10.1109/ISCAS.2019.8702159

Effective AM-PM cancellation with body bias for 5G CMOS power amplifier design in 22nm FD-SOI. / Mayeda, Jill C.; Tsay, Jerry; Lie, Donald Y.C.; Lopez, Jerry.

2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. 8702159 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Tsay, Jerry

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N2 - Novel linearity enhancement using body bias tuning for 24-28 GHz CMOS SOI power amplifier (PA) design is reported. The differential PA is designed, laid out, and taped out in an advanced 22nm fully-depleted silicon-on-insulator (FD-SOI) technology, which utilizes stacked FETs, digitally-controlled neutralization capacitors, interstage matching and output matching capacitors with on-chip baluns to cover 24-28 GHz for potential 5G applications. Post-layout SPICE simulations show the AM-PM distortion at Pout,1dB can be reduced to only < 0.1° by body bias tuning of the 2nd stage FETs alone, with power-added-efficiency (PAE) at Pout,1dB at 24.1%/17.5% with high S21 =26.5/22.1 dB at 24GHz/28GHz. Using 64-QAM 250 MHz modulated input signal, this PA design has also achieved an ACLR1 of ~ -24.5/-28.5 dBc at Pout = 11.7/9.5 dBm in post-layout simulation at 28 GHz, and with the smallest core PA die area in the literature. We believe this is the 1st report of very effective AM-PM cancellation for mm-Wave CMOS SOI PA design using positive body biasing.

AB - Novel linearity enhancement using body bias tuning for 24-28 GHz CMOS SOI power amplifier (PA) design is reported. The differential PA is designed, laid out, and taped out in an advanced 22nm fully-depleted silicon-on-insulator (FD-SOI) technology, which utilizes stacked FETs, digitally-controlled neutralization capacitors, interstage matching and output matching capacitors with on-chip baluns to cover 24-28 GHz for potential 5G applications. Post-layout SPICE simulations show the AM-PM distortion at Pout,1dB can be reduced to only < 0.1° by body bias tuning of the 2nd stage FETs alone, with power-added-efficiency (PAE) at Pout,1dB at 24.1%/17.5% with high S21 =26.5/22.1 dB at 24GHz/28GHz. Using 64-QAM 250 MHz modulated input signal, this PA design has also achieved an ACLR1 of ~ -24.5/-28.5 dBc at Pout = 11.7/9.5 dBm in post-layout simulation at 28 GHz, and with the smallest core PA die area in the literature. We believe this is the 1st report of very effective AM-PM cancellation for mm-Wave CMOS SOI PA design using positive body biasing.

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KW - FD-SOI

KW - Millimeter-wave

KW - Reconfigurable PA

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M3 - Conference contribution

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BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

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Mayeda JC, Tsay J, Lie DYC, Lopez J. Effective AM-PM cancellation with body bias for 5G CMOS power amplifier design in 22nm FD-SOI. In 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. 8702159. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2019.8702159