TY - GEN
T1 - Design of an automated test bed for experimental Si and SiC SGTO devices
AU - Lawson, Kevin
AU - Lacouture, Shelby
AU - Bayne, Stephen B.
AU - Giesselmann, Michael
AU - Vollmer, Travis
AU - O'Brien, Heather
AU - Scozzie, Charles
AU - Ogunniyi, Aderinto
PY - 2012
Y1 - 2012
N2 - In a collaborative effort between Army Research Lab (ARL) and Texas Tech University's center for Pulsed Power and Power Electronics (P3E) lab, a high power, high energy test bed meant to characterize experimental Si and SiC Super Gate Turn Off (SGTO) devices was designed and built. The system was engineered to run the devices through an arbitrary number of test cycles while recording all pertinent data automatically. Test parameters are set through a windows GUI which communicates with a microprocessor based control system that orchestrates timing and settings of each subsystem as well as acquiring voltage and current waveforms with high speed ADCs operating simultaneously in parallel. The test waveform itself is generated by a Pulse Forming Network (PFN) which accurately controls rise time, fall time and pulse width. The PFN is charged by a Rapid Capacitor Charger (RCC) system designed at the P3E lab that is capable of 10 kW and allows precise charge voltage levels to be set. Waveforms are acquired through isolated probes specifically designed to capture desired signals even in the presence of a large bias voltages.
AB - In a collaborative effort between Army Research Lab (ARL) and Texas Tech University's center for Pulsed Power and Power Electronics (P3E) lab, a high power, high energy test bed meant to characterize experimental Si and SiC Super Gate Turn Off (SGTO) devices was designed and built. The system was engineered to run the devices through an arbitrary number of test cycles while recording all pertinent data automatically. Test parameters are set through a windows GUI which communicates with a microprocessor based control system that orchestrates timing and settings of each subsystem as well as acquiring voltage and current waveforms with high speed ADCs operating simultaneously in parallel. The test waveform itself is generated by a Pulse Forming Network (PFN) which accurately controls rise time, fall time and pulse width. The PFN is charged by a Rapid Capacitor Charger (RCC) system designed at the P3E lab that is capable of 10 kW and allows precise charge voltage levels to be set. Waveforms are acquired through isolated probes specifically designed to capture desired signals even in the presence of a large bias voltages.
KW - Power semiconductor switches
KW - Pulse forming network
KW - Pulse power system switches
KW - Pulse shaping circuits
KW - Silicon
KW - Silicon carbide
KW - Thyristors
UR - http://www.scopus.com/inward/record.url?scp=84879921729&partnerID=8YFLogxK
U2 - 10.1109/IPMHVC.2012.6518751
DO - 10.1109/IPMHVC.2012.6518751
M3 - Conference contribution
AN - SCOPUS:84879921729
SN - 9781467312233
T3 - Proceedings of the 2012 IEEE International Power Modulator and High Voltage Conference, IPMHVC 2012
SP - 347
EP - 350
BT - Proceedings of the 2012 IEEE International Power Modulator and High Voltage Conference, IPMHVC 2012
T2 - 2012 IEEE International Power Modulator and High Voltage Conference, IPMHVC 2012
Y2 - 3 June 2012 through 7 June 2012
ER -