Circuit and system design for a homodyne W-CDMA front-end receiver RFIC

D. Y.C. Lie, J. Kennedy, D. Livezey, B. Yang, T. Robinson, N. Sornin, C. Saint, L. E. Larson

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper discusses the RF circuit and system design considerations for W-CDMA homodyhe receiver on NF, IIP2, IIP3, LO/TX leakage, I-Q mismatch, DC offsets, etc. A zero-IF receiver front-end SiGe BiCMOS IC is designed, packaged and thoroughly characterized by a set of system-level performance tests across the full frequency band of operation. The measured worst-case cascaded NF for the receiver IC across all channels is 4.3 dB at the max. gain mode, and the in-band/out-of-band IIP2 and IIP3 are +37/+93 and -16.5/+5 dBm, respectively. The I/Q channels exhibit a small mismatch in magnitude (<0.1dB) and in phase (<1°) without calibration. The receiver RF front-end (i.e., LNA+VGA+ I/Q mixers) draws ∼45mW. The system tests results on BER, P1dB, IM2, IM3, and desensing show mat the RFIC meets all of the necessary parameters of W-CDMA receiver system specs at room temperature with margin, validating the RF IC block-level circuit design and providing valuable RF-SoC design insights.

Original languageEnglish
Title of host publication2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages25-28
Number of pages4
DOIs
StatePublished - 2007
Event2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan, Province of China
Duration: Apr 26 2007Apr 28 2007

Publication series

Name2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
CountryTaiwan, Province of China
CityHsinchu
Period04/26/0704/28/07

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