Analysis of SiC JFET devices during pulsed operation

K. Lawson, G. Alvarez, S. Bayne, V. Veliadis, D. Urciuoli

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations


The purpose of this research is to investigate the performance of Silicon Carbide JFET for us in solid state circuit breakers. The device under test for these results is a research grade JFET with a rated blocking voltage of 1200V and a rated forward current of 10A with a power density of 200W/cm 2. In order to drive the JFET device, a unique gate driver had to be designed and built to provide switching between two independent rail voltages. The gate driver had to be able to provide adjustable rail voltages with one rail ranging between 0V and -40V and the other rail going between 0V and 2.5V. The gate driver is completely isolated to operate on a high-side switch. In order to test these devices in pulsed switching applications a pulse ring down circuit was designed and built to provide a current pulse of 100A (10 times the rated current) with a charging voltage range between 100V and 500V. Special consideration had to be given to the design of this pulse ring down circuit in order to achieve a high di/dt, and therefore reach the target peak current levels.

Original languageEnglish
Title of host publicationIEEE Conference Record - PPC 2011, Pulsed Power Conference 2011
Subtitle of host publicationThe 18th IEEE International Pulsed Power Conference
Number of pages3
StatePublished - 2011
Event18th IEEE International Pulsed Power Conference, PPC 2011 - Chicago, IL, United States
Duration: Jun 19 2011Jun 23 2011

Publication series

NameDigest of Technical Papers-IEEE International Pulsed Power Conference


Conference18th IEEE International Pulsed Power Conference, PPC 2011
Country/TerritoryUnited States
CityChicago, IL


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