TY - JOUR
T1 - An 8-bit single-ended ultra-low-power SAR ADC with a novel DAC switching method and a counter-based digital control circuitry
AU - Hu, Weibo
AU - Liu, Yen Ting
AU - Nguyen, Tam
AU - Lie, Donald Y.C.
AU - Ginsburg, Brian P.
PY - 2013
Y1 - 2013
N2 - This paper proposes a design of ultra-low-power successive approximation register (SAR) analog-to-digital converters (ADC) specially optimized for very low frequency biosensor applications. Two new techniques are introduced: 1) a novel digital-to-analog converter (DAC) switching method suitable for single-ended SAR ADCs; and 2) a counter-based digital control circuitry. The DAC switching method uses VR/2 as an only reference voltage to digitize the input signals within [0, VR], and reduces the power consumption in the DAC during digitizing by 87.5% versus the traditional one. The counter-based controller can reduce power consumption in the digital circuitry by 30%. Two prototype 8-bit SAR ADCs are designed, one in a TI 0.35-μm Bipolar-CMOS-DMOS (BCD) process and the other in a TSMC 0.18-μm CMOS process. The 0.35-μm ADC consumes 101 nW, and achieves a signal to noise and distortion ratio (SNDR) of 48.2 dB and a figure of merit (FOM) of 227 fJ/conversion-step at 2 kS/s. The 0.18-μm ADC can achieve a SNDR of 46.3 dB with only 27 nW and a FOM of 79.9 fJ/conversion-step at 2 kS/s.
AB - This paper proposes a design of ultra-low-power successive approximation register (SAR) analog-to-digital converters (ADC) specially optimized for very low frequency biosensor applications. Two new techniques are introduced: 1) a novel digital-to-analog converter (DAC) switching method suitable for single-ended SAR ADCs; and 2) a counter-based digital control circuitry. The DAC switching method uses VR/2 as an only reference voltage to digitize the input signals within [0, VR], and reduces the power consumption in the DAC during digitizing by 87.5% versus the traditional one. The counter-based controller can reduce power consumption in the digital circuitry by 30%. Two prototype 8-bit SAR ADCs are designed, one in a TI 0.35-μm Bipolar-CMOS-DMOS (BCD) process and the other in a TSMC 0.18-μm CMOS process. The 0.35-μm ADC consumes 101 nW, and achieves a signal to noise and distortion ratio (SNDR) of 48.2 dB and a figure of merit (FOM) of 227 fJ/conversion-step at 2 kS/s. The 0.18-μm ADC can achieve a SNDR of 46.3 dB with only 27 nW and a FOM of 79.9 fJ/conversion-step at 2 kS/s.
KW - Analog-to-digital converter (ADC)
KW - digital-to-analog converter (DAC)
KW - successive approximation register (SAR) ADC
KW - ultra-low-power sensor
UR - http://www.scopus.com/inward/record.url?scp=84880070292&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2012.2230587
DO - 10.1109/TCSI.2012.2230587
M3 - Article
AN - SCOPUS:84880070292
SN - 1549-8328
VL - 60
SP - 1726
EP - 1739
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 7
M1 - 6547197
ER -