A taxonomy of data prefetching mechanisms

Surendra Byna, Yong Chen, Xian He Sun

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

22 Scopus citations

Abstract

Data prefetching has been considered an effective way to mask data access latency caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been proposed in the last few years to reduce data access latency by taking advantage of multi-core architectures. In this paper, we propose a taxonomy that classifies various design concerns in developing a prefetching strategy. We discuss various prefetching strategies and issues that have to be considered in designing a prefetching strategy for multi-core processors.

Original languageEnglish
Title of host publicationProceedings - 9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008
Pages19-24
Number of pages6
DOIs
StatePublished - 2008
Event9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008 - Sydney, NSW, Australia
Duration: May 7 2008May 9 2008

Publication series

NameProceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN

Conference

Conference9th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2008
CountryAustralia
CitySydney, NSW
Period05/7/0805/9/08

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