A radiation-tolerant ring oscillator phase-locked loop in 0.13μm CMOS

Advanced CMOS technologies have demonstrated reduced sensitivity to radiation total-ionization-dose (TID) effect. However, the reduced device dimensions can significantly increase the circuit sensitivity to transient radiation effects. This paper presents a radiation-tolerant ring oscillator Phase-Locked Loop (PLL) designed in a commercial 0.13 μm CMOS process. The PLL is designed for radiation-tolerant high-speed serial link applications. It operates over a frequency range of 1.1 GHz to 4.4 GHz with an RMS jitter of 1.8 ps at 3.125 GHz. The phase frequency detector (PFD) and frequency divider (FD) are designed with a novel D-flip-flop (DFF) that is robust to single event radiation effects (SEEs). The voltage-controlled oscillator (VCO) is designed with two ring oscillators cross-coupled thus compensating each other with the radiation-induced transient currents. Each ring oscillator has its own control voltage driven by an independent charge pump and loop filter. The redundancy helps to mitigate radiation strikes on the VCO control voltage. Simulation results show that the proposed PLL demonstrates radiation immunity for critical charge values up to 250 fC and can recover quickly from radiation strikes on its sensitive nodes. The PLL operates under a 1.2 V power supply and consumes 40 mW of power.