A Power-optimized Reconfigurable CT ΔΣ Modulator in 65nm CMOS

R. Wang; K. Azadet; Changzhi Li; Jinghong Chen; Xiaoke Wen

doi:10.1109/ISCAS.2012.6271963

A Power-optimized Reconfigurable CT ΔΣ Modulator in 65nm CMOS

R. Wang, K. Azadet, Changzhi Li, Jinghong Chen, Xiaoke Wen

Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

This paper presents transistor-level design of a continuous-time (CT) reconfigurable ΔΣ modulator in a 1.2 V 65 nm CMOS process. Both architectural-and circuit-level power-optimization techniques, such as flexible loop order and quantizer bit, switchable OTA unit cells, and folding flash ADC, are utilized to achieve power efficiency over all bandwidths. As gate leakage current in 65 nm technology becomes prominent, a DAC biasing scheme that is robust to gate leakage current is employed. Simulation results show that the modulator achieves signal-to-noise-and-distortion-ratio (SNDR) of 73.3/76.5/77.4/84.4 dB for 20/10/3/0.5 MHz bandwidth (BW) with power consumption of 23.9/20.7/9.49/7.22 mW, respectively. The respective figure of merit (FOM) equals 0.16/0.19/0.26/0.53 pJ/conv.

Original language	English
Pages	305-308
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271963
State	Published - May 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: May 20 2012 → May 23 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	05/20/12 → 05/23/12

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10.1109/ISCAS.2012.6271963

Cite this

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title = "A Power-optimized Reconfigurable CT ΔΣ Modulator in 65nm CMOS",

abstract = "This paper presents transistor-level design of a continuous-time (CT) reconfigurable ΔΣ modulator in a 1.2 V 65 nm CMOS process. Both architectural-and circuit-level power-optimization techniques, such as flexible loop order and quantizer bit, switchable OTA unit cells, and folding flash ADC, are utilized to achieve power efficiency over all bandwidths. As gate leakage current in 65 nm technology becomes prominent, a DAC biasing scheme that is robust to gate leakage current is employed. Simulation results show that the modulator achieves signal-to-noise-and-distortion-ratio (SNDR) of 73.3/76.5/77.4/84.4 dB for 20/10/3/0.5 MHz bandwidth (BW) with power consumption of 23.9/20.7/9.49/7.22 mW, respectively. The respective figure of merit (FOM) equals 0.16/0.19/0.26/0.53 pJ/conv.",

author = "R. Wang and K. Azadet and Changzhi Li and Jinghong Chen and Xiaoke Wen",

year = "2012",

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doi = "10.1109/ISCAS.2012.6271963",

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pages = "305--308",

note = "2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 ; Conference date: 20-05-2012 Through 23-05-2012",

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AU - Wang, R.

AU - Azadet, K.

AU - Li, Changzhi

AU - Chen, Jinghong

AU - Wen, Xiaoke

PY - 2012/5

Y1 - 2012/5

N2 - This paper presents transistor-level design of a continuous-time (CT) reconfigurable ΔΣ modulator in a 1.2 V 65 nm CMOS process. Both architectural-and circuit-level power-optimization techniques, such as flexible loop order and quantizer bit, switchable OTA unit cells, and folding flash ADC, are utilized to achieve power efficiency over all bandwidths. As gate leakage current in 65 nm technology becomes prominent, a DAC biasing scheme that is robust to gate leakage current is employed. Simulation results show that the modulator achieves signal-to-noise-and-distortion-ratio (SNDR) of 73.3/76.5/77.4/84.4 dB for 20/10/3/0.5 MHz bandwidth (BW) with power consumption of 23.9/20.7/9.49/7.22 mW, respectively. The respective figure of merit (FOM) equals 0.16/0.19/0.26/0.53 pJ/conv.

AB - This paper presents transistor-level design of a continuous-time (CT) reconfigurable ΔΣ modulator in a 1.2 V 65 nm CMOS process. Both architectural-and circuit-level power-optimization techniques, such as flexible loop order and quantizer bit, switchable OTA unit cells, and folding flash ADC, are utilized to achieve power efficiency over all bandwidths. As gate leakage current in 65 nm technology becomes prominent, a DAC biasing scheme that is robust to gate leakage current is employed. Simulation results show that the modulator achieves signal-to-noise-and-distortion-ratio (SNDR) of 73.3/76.5/77.4/84.4 dB for 20/10/3/0.5 MHz bandwidth (BW) with power consumption of 23.9/20.7/9.49/7.22 mW, respectively. The respective figure of merit (FOM) equals 0.16/0.19/0.26/0.53 pJ/conv.

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T2 - 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012

Y2 - 20 May 2012 through 23 May 2012

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A Power-optimized Reconfigurable CT ΔΣ Modulator in 65nm CMOS

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