A power-optimized reconfigurable CT ΔΣ modulator in 65nm CMOS

Rui Wang, Xiaoke Wen, Kamran Azadet, Changzhi Li, Jinghong Chen

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

This paper presents transistor-level design of a continuous-time (CT) reconfigurable ΔΣ modulator in a 1.2 V 65 nm CMOS process. Both architectural-and circuit-level power-optimization techniques, such as flexible loop order and quantizer bit, switchable OTA unit cells, and folding flash ADC, are utilized to achieve power efficiency over all bandwidths. As gate leakage current in 65 nm technology becomes prominent, a DAC biasing scheme that is robust to gate leakage current is employed. Simulation results show that the modulator achieves signal-to-noise-and-distortion-ratio (SNDR) of 73.3/76.5/77.4/84.4 dB for 20/10/3/0.5 MHz bandwidth (BW) with power consumption of 23.9/20.7/9.49/7.22 mW, respectively. The respective figure of merit (FOM) equals 0.16/0.19/0.26/0.53 pJ/conv.

Original languageEnglish
Pages305-308
Number of pages4
DOIs
StatePublished - 2012
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: May 20 2012May 23 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/TerritoryKorea, Republic of
CitySeoul
Period05/20/1205/23/12

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